Systemverilog Assertions and Functional Coverage: Guide to Language, Methodology

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Specifiche dell'oggetto

Condizione
Nuovo: Libro nuovo, intatto e non letto, in perfette condizioni, senza pagine mancanti o ...
Book Title
Systemverilog Assertions and Functional Coverage: Guide to Langua
Publication Date
2013-08-06
Pages
356
ISBN
9781461473237
Categoria

Informazioni su questo prodotto

Product Identifiers

Publisher
Springer New York
ISBN-10
1461473233
ISBN-13
9781461473237
eBay Product ID (ePID)
160068249

Product Key Features

Number of Pages
Xxxiii, 356 Pages
Language
English
Publication Name
Systemverilog Assertions and Functional Coverage : Guide to Language, Methodology and Applications
Subject
Systems Architecture / General, Electronics / Circuits / General, Electronics / General, Logic Design, Computer Engineering
Publication Year
2013
Type
Textbook
Subject Area
Computers, Technology & Engineering
Author
Ashok B. Mehta
Format
Hardcover

Dimensions

Item Height
0.3 in
Item Weight
250.3 Oz
Item Length
9.3 in
Item Width
6.1 in

Additional Product Features

Intended Audience
Scholarly & Professional
Number of Volumes
1 vol.
Illustrated
Yes
Table Of Content
Introduction.- System Verilog Assertions.- Immediate Assertions.- Concurrent Assertions - Basics (sequence, property, assert).- Sampled Value Functions $rose, $fell.- Operators.- System Functions and Tasks.- Multiple clocks.- Local Variables.- Recursive property.- Detecting and using endpoint of a sequence.- 'expect'.- 'assume' and formal (static functional) verification.- Other important topics.- Asynchronous Assertions !!!.- IEEE-1800-2009 Features.- SystemVerilog Assertions LABs.- System Verilog Assertions - LAB Answers.- Functional Coverage.- Performance Implications of coverage methodology.- Coverage Options (Reference material).
Synopsis
This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug., This book offers a hands-on, application-oriented guide to the language and methodology of SystemVerilog Assertions and SystemVerilog Functional Coverage. Includes easy-to-understand examples, simulation logs and applications derived from real-world projects.
LC Classification Number
TK7867-7867.5

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    Book was "nearly new" and "as described" in listing. The advertised price was fair and a good value. Unfortunately, the seller's shipping partner was very slow to get the book packaged and shipped. Shipping took too long, and the tracking info gave no reliable info on shipping date, time in transit or expected delivery. Seller did everything right, but their shipping partner needs improvement. I recommend this seller to other eBay buyers....... just make sure you're okay with the shipping terms.
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